IBM and Lam Research announced on March 10 a new collaboration to develop processes and materials for sub-1 nanometer (nm) logic scaling. The five-year agreement aims to extend logic scaling beyond current limits by focusing on novel materials, advanced etch and deposition capabilities, and High-NA EUV lithography processes.
The partnership is significant as it addresses the increasing complexity of semiconductor device architectures and the industry’s need for continued performance improvements. By working together, IBM and Lam Research hope to accelerate the adoption of next-generation interconnects and device patterning necessary for future chip technologies.
Mukesh Khare, GM of IBM Semiconductors and VP of Hybrid Cloud at IBM Research, said, “Lam has been a critical partner to IBM for over a decade, contributing to key breakthroughs in logic scaling and device architecture such as nanosheet and the world’s first 2nm node chip, unveiled by IBM in 2021. We are thrilled to be expanding our collaboration to tackle the next set of challenges to enable High-NA EUV lithography and sub-1nm nodes.”
Vahid Vahedi, chief technology and sustainability officer at Lam Research, said, “As the industry enters a new era of 3D scaling, progress depends on rethinking how materials, processes, and lithography come together as a single, high-density system. We are proud to build on our successful collaboration with IBM to drive High‑NA EUV dry resist and process breakthroughs, accelerating the development of lower power and higher performance transistors that will be critical for AI era.”
The joint effort will use IBM’s research facilities at NY Creates Albany NanoTech Complex along with Lam’s process tools such as Aether dry resist technology, Kiyo and Akara etch platforms, Striker and ALTUS Halo deposition systems. These resources will help validate full process flows for nanosheet devices as well as backside power delivery techniques.
This collaboration reflects ongoing efforts within the semiconductor industry to overcome technical barriers in chip manufacturing while enabling more powerful computing solutions.
